82503 Datasheet, PDF (37/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
LOOPBACK TIMINGS
Symbol
Parameter
Min
Typ
Max
Units
t₁₅₅
TxD to RxD Bit Loss at Start of Packet
16
bits
t₁₅₆
TxD to RxD Steady State Propagation Delay
600
ns
t₁₅₇
TxD to RxD Startup Delay
22
ms
t₁₅₈
SQE Test Wait Time
06
12
16
ms
t₁₅₉
SQE Test Duration
05
08
15
ms
t₁₆₀
LPBK Setup Hold Times to RTS⁽²²⁾
10
ms
NOTE
22 Guarantees proper processing of transmitted packets Violation of this specification will not result in spurious data trans-
mission Incoming data packets occuring during transitions on LPBK will not be accepted
Figure 38 Loopback Timings
290421 – 37
37