82503 Datasheet, PDF (22/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
AC TIMING CHARACTERISTICS (Continued)
290421 – 12
Figure 13 Voltage Levels for
TDH TDL TDH and TDL
290421 – 13
Figure 14 Voltage Levels for Differential Input
Timing Measurements (RD Pair)
AC MEASUREMENT CONDITIONS
1 T_C ^e 0 C to ^a85 C V_CC ^e 5V g5%
2 The AC MOS TTL and differential signals are referred to in Figures 8 9 10 11 12 and 13
3 AC loads
a MOS 20 pF total capacitance to ground
b AUI Differential a 10 pF total capacitance from each terminal to ground and a load resistor of 78X g1%
in parallel with a 27 mH g1% inductor between terminals
c TPE 20 pF total capacitance to ground
4 All parameters become valid 200 ms after the supply voltage and input clock has stabilized or after RESET
deasserts
CLOCK TIMING ⁽¹⁵⁾
Symbol
Parameter
Min
Typ
Max
Units
t₁
X1 Cycle Time
49 995
t₂
X1 Fall Time
t₃
X1 Rise Time
t₄
X1 Low Time
15
t₅
X1 High Time
15
50 005
ns
5
ns
5
ns
ns
ns
NOTE
15 Refers to External Clock Input
Figure 15 X1 Input Voltage Levels for Timing Measurements
290421 – 14
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