82503 Datasheet, PDF (27/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
Controller Interface Timing (AMD Mode)
TRANSMIT TIMINGS⁽¹⁸⁾ (AMD)
Symbol
Parameter
Min
Typ
Max
t₅₀
TCLK Cycle Time
99 99
100 01
t₅₁
TCLK High Time ( 0 8V to 2 0V)
45
50
58
t₅₂
TCLK Low Time ( 2 0V to 0 8V)
45
50
58
t₅₃
TCLK Rise Fall Time ( 0 8V to 2 0V)
25
5
t₅₄
u TX Setup Time to TCLK
20
t₅₅
u TX Hold Time from TCLK
5
t₅₆
u TENA Setup Time to TCLK
20
t₅₇
u TENA Hold Time from TCLK
5
NOTE
18 Delay times for TX TENA and TCLK are measured from 0 8V for falling edges and 2 0V for rising edges
Units
ns
ns
ns
ns
ns
ns
ns
ns
Figure 20 Transmit Timings (AMD)
290421 – 19
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