82503 Datasheet, PDF (32/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
Figure 28 TPE Transmit Timings (Link Test Pulse)
290421 – 27
TPE RECEIVE TIMINGS
Symbol
Parameter
Min Typ
Max
Units
t₁₀₅
RD to RxD Bit Loss at Start of Packet
4
t₁₀₆
RD to RxD Invalid Bits Allowed at Start of Packet
t₁₀₇
RD to RxD Steady State Propagation Delay
t₁₀₈
RD to RxD Start UP Delay
t₁₀₉
RD Pair Bit Cell Center Jitter
t₁₁₀
RD Pair Bit Cell Boundary Jitter
t₁₁₁
RD Pair Held High from Last Valid Positive Transition 230
t₁₁₂
CRS Assertion Delay (Intel NS and Fuji Mode)
(AMD Mode)
19
bits
1
bits
400
ns
24
ms
g13 5
ns
g13 5
ns
400
ns
700
ns
1500
ns
t₁₁₃
CRS Deassertion Delay
450
ns
Figure 29 TPE Receive Timings (Start of Frame)
290421 – 28
32