82503 Datasheet, PDF (28/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
RECEIVE TIMINGS⁽¹⁹⁾ (AMD)
Symbol
Parameter
Min
Typ
Max
t₆₀
RCLK Cycle Time
96
100
t₆₁
RCLK High Time ( 0 8V to 2 0V)
38
50
t₆₂
RCLK Low Time ( 2 0V to 0 8V)
38
50
t₆₃
RCLK Rise Fall Time ( 0 8V to 2 0V)
25
5
t₆₄
RX Rise Fall Time ( 0 8V to 2 0V)
25
5
t₆₅
u RX Hold time from RCLK
10
t₆₆
u RX Setup Time to RCLK
45
t₆₇
u RENA Deassertion Hold Time from RCLK
40
50
80
t₆₈
u RCLK Delay from RENA
450
NOTE
19 Delay times for RX RENA and RCLK are measured from 0 8V for falling edges and 2 0V for rising edges
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 21 Receive Timings (AMD Start of Frame)
290421 – 20
Figure 22 Receive Timings (AMD End of Frame)
290421 – 21
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