82503 Datasheet, PDF (10/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
3 0 82503 ARCHITECTURE
3 1 Clock Generation
A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator which provides the
basic 20 MHz clock source An internal divide-by-
two counter generates the 10 MHz g0 01% clock
required by the IEEE 802 3 specification
We recommend a crystal that meets the following
specifications be used
 Quartz Crystal
 20 MHz g 0 002% at 25 C
 Accuracy g 0 005% over full operating tempera-
ture 0 C to ^a70 C
 Parallel resonant with 20 pF Load Fundamental
Mode
 Maximum Series Resistance R_SERIES ^e 30X
Several vendors have such crystals either-off-the
shelf or custom made Two possible vendors are
1 M-Tron Industries Inc
Yankton SD 57078
Specifications
Part No HC49 with 20 MHz 50 PPM over 0 C to
a_{70 C and 20 pF fundamental load}
2 Crystek Corporation
100 Crystal Drive
Ft Myers FL 33907
Part No 013212
The accuracy of the Crystal Oscillator frequency de-
pends on the PC board characteristics therefore it is
advisable to keep the X1 and X2 traces as short as
possible The optimum value of C1 and C2 should
be determined experimentally under nominal operat-
ing conditions The typical value of C1 and C2 is
between 22 pF and 35 pF
An external 20 MHz MOS-level clock may be applied
to pin X1 if pin X2 is left floating
3 2 Transmit Blocks
3 2 1 MANCHESTER ENCODER
The 20 MHz clock is used to Manchester-encode
data on the TxD input This clock is also divided by
two to produce the 10 MHz clock the LAN controller
needs for synchronizing its RTS and TxD signals
Data encoding and transmission begins with RTS
asserting Since the first bit of a transmission is a 1
the first transition is always negative on the transmit
outputs (TRMT or TD pins) Transmission ends
when RTS deasserts The last transition is always
positive at the transmit outputs (TRMT or TD pins)
and may occur at the center of the bit cell if the last
data bit to be transmitted is a 1 or at the boundary
of the bit cell if the last data bit to be sent is a 0
Immediately after the end of a transmission all sig-
nals on the RCV pair (when AUI mode is selected)
are inhibited for 4 to 5 ms This dead time is neces-
sary for proper operation of the SQE (heartbeat)
test
3 2 2 AUI CABLE DRIVER
The AUI cable driver (TRMT pair) is a differential
circuit which interfaces to the AUI cable through a
pulse transformer
High voltage protection is achieved by using a trans-
former to isolate the transmit pins (TRMT pair) from
the transceiver cable The total transmit circuit in-
ductance including the 802 3 transceiver transform-
ers should be a minimum of 27 mH for Ethernet ap-
plications
3 2 3 TWISTED PAIR CABLE DRIVER
The twisted pair line drivers (TD pairs) begin trans-
mitting the serial Manchester bit stream 3 bit times
after RTS is asserted The line drivers use a predis-
tortion algorithm to improve jitter performance for up
to 100 meters of twisted pair cable The line drivers
reduce their drive level during the second half of
‘‘fat’’ (100 ns) Manchester pulses and maintain a full
drive level during all ‘‘thin’’ (50 ns) pulses and during
the first half of the ‘‘fat’’ pulses This reduces line
overcharging during ‘‘fat’’ pulses a major source of
jitter
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