82503 Datasheet, PDF(17/45 Page) Intel Corporation

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82503 Datasheet, PDF (17/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

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82503

RESET

TEST

Table 3 Test and Low Power Mode Selection

JABD

TxLED(1)

RxLED(1)

COLED(1)

Mode Selected

Normal Mode

Cont Tx 10 MHz

Low Power

NOTE

1 A standard LED connection to these pins is sufficient to pull them to a logic 1

The port on which the continuous transmit appears

is determined by the APORT and TPE AUI pins If

automatic port selection is enabled (APORT e 1)

then the TPE port broadcasts the continuous trans-

mit If manual port selection is enabled (APORT e

0) then TPE AUI selects the port (1 for TPE 0 for

AUI) Test mode is disabled when TEST is deassert-

ed and the device is reset

5 0 APPLICATION EXAMPLE

5 1 Introduction

The 82503 is designed to work directly with the Intel

LAN controllers (82586 82590 82593 and 82596)

as well as AMDâs Am7990 National Semiconduc-

torâs 8390 Western Digitalâs 82C690 and Fujitsuâs

86950 The serial interface signals connect directly

between one of the aforementioned LAN controllers

and the 82503 without the need for external logic

This example is targeted toward interfacing the

82503 to the Intel 82596 in a two-port (TPE AUI)

application

5 2 Design Guidelines

AUI Pulse Transformer

In order to meet the 16V fault tolerance specification

of 802 3 a pulse transformer is recommended for the

transmit receive and collision pairs The transformer

should be placed between the TRMT RCV and

CLSN pairs of the 503 and the DO DI and CI pairs

respectively of the AUI (DB-15 connector) The

pulse transformer should have a parallel inductance

of 75 mH minimum (100 mH recommended)

Several vendors stock such transformers Two pos-

sible vendors are

1 Pulse Engineering (P N PE-64103)

2 Valor Electronics (P N LT6003)

Terminating Resistors

The terminating resistors used across the receive

and collision pairs are recommended to be 78 7 X

g1%

Analog Front-End

The 82503 provides six TPE pins (TDH TDH TDL

TDL RD and RD) that connect to the Analog Front

End through a resistor summing network (Figure 7)

AFE solutions can be made discretely or purchased

from several manufacturers Two different solutions

are described in Application Note 356 The example

shown here uses a Pulse Engineering AFE package

PE65434 which includes EMI filter isolation trans-

former and common mode choke The output of the

AFE connects directly to the 10BASE-T connector

(RJ-45)

Decoupling

It is recommended that 0 01 mF X7R and 0 001 mF

NPO decoupling capacitors be placed between the

VCCA and VCCD of the 82503 to VSSA and VSSD

Clock Generation

The clock input to the 82503 can be from a clock

oscillator or a crystal If a clock oscillator is used X1

should be driven and X2 left floating If a crystal

oscillator is used refer to Section 3 1 for crystal

specifications

A complete 82596 82503 TPE AUI Ethernet Solu-

tion is shown at the end of this section

5 3 Layout Guidelines

General

The analog section as well as the entire board itself

should conform to good high-frequency practices

and standards to minimize switching transients and

parasitic interaction between various circuits To

achieve this the following guidelines are presented

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