82503 Datasheet, PDF (31/45 Pages) Intel Corporation – DUAL SERIAL TRANSCEIVER (DST)

82503
TPE Timings
TPE TRANSMIT TIMINGS
Symbol
Parameter
Min Typ Max Units
t₉₀
TxD to TD Bit Loss at Start of Packet
2
bits
t₉₁
TxD to TD Steady State Propagation Delay
400
ns
t₉₂
TxD to TD Startup Delay
600
ns
t₉₃
TDH and TDL Pairs Edge Skew ( V_CC 2)
15
3
ns
t₉₄
TDH and TDL Pairs Rise Fall Times ( 0 5V to V_CC ^b 0 5V)
2
5
ns
t₉₅
TDH and TDL Pairs Bit Cell Center to Center
99 100 101
ns
t₉₆
TDH and TDL Pairs Bit Cell Center to Boundary
49
50
51
ns
t₉₇
u TDH and TDL Pairs Return to Zero from Last TDH
250
400
ns
t₉₈
Link Test Pulse Width
98 100 102
ns
t₉₉
Last TD Activity to Link Test Pulse
8
13
24
ms
t₁₀₀
Link Test Pulse to Data Separation
190 200
ns
Figure 26 TPE Transmit Timings (Start of Frame)
290421 – 25
Figure 27 TPE Transmit Timings (End of Frame)
290421 – 26
31