NQ41210SL7JE Datasheet, PDF (36/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
3.5.4.1
2. The average period over any 1 us period of time must be greater than the minimum specified period.
3. T_high is measured at 2.4V for non-host outputs.
4. T_low is measured at 0.4V for all outputs.
5. For 3.3V clocks T_rise and T_fall are measured as a transition through the threshold region V_ol = 0.4V and V_oh =
2.4V (1 mA) JEDEC Specification.
6. Measured at crossing point.
7. Measured from V_ol = 0.2V to V_oh = 0.8V.
8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].
9. Determined as a fraction of 2*(T_rise – T_fall) / (T_rise + T_fall).
10.Period jitter is the deviation between any single period of the clock, T_cyc, and the average period of the clock,
T_cyc(average).
Spread Spectrum Clocking
Spread spectrum clocking can be used on the 41210 Bridge to reduce energy. Spread Spectrum
clocking is a common technique used by system designers to meet FCC emissions, where the
frequency is deliberately shifted around to spread the energy off of the peak. The following is to be
observed when using Spread Spectrum clocking:
• All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST
meet the existing non-spread spectrum specifications
• All non-spread Host and PCI functionality must be maintained in the spread spectrum mode
(includes all power management functions.)
• The minimum clock period cannot be violated. The preferred method is to adjust the spread
technique to not allow for modulation above the nominal frequency. This technique is often
called “down-spreading”. The modulation profile in a modulation period can be expressed as:
Equations:
f

=


(1 − δ ) f _nom
+ 2 f_m
⋅δ
⋅
f _nom
⋅t
₍₁

+
δ
)
f _nom
−
2
f_m
⋅δ
⋅
f _nom
⋅t
when 0 < t < ¹ ;
2 f_m
when ¹ < t < ¹ ,
2 f_m
f_m
where:
f_nom is the nominal frequency in the non-SSC mode
f_m is the modulation frequency
f_m is the modulation amount
t is time.
3.6
41210 Bridge Power Consumption
Table 28 provides details on the maximum draw from the power planes by the 41210 Bridge for
use in voltage regulation.
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