NQ41210SL7JE Datasheet, PDF (22/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
Figure 1. Minimum Transmitter Timing and Voltage Output Compliance Specification
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be
aligned in time using the jitter median to locate the center of the eye diagram. The different eye
diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit.
The eye diagram must be valid for any 250 consecutive UIs. An appropriate average TX UI must
be used as the interval for measuring the eye diagram.
3.1.6.3
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified by
the device vendor within 0.2 inches of the package pins, into a test/measurement load shown in
Figure 2.
Note: The allowance of the measurement point to be within 0.2 inches of the package pins is meant to
acknowledge that package/board routing may benefit from D+ and D- not being exactly matched in length at
the package pin boundary. If the vendor does not explicitly state where the measurement point is located, the
measurement point is assumed to be the D+ and D-package pins.
22