NQ41210SL7JE Datasheet, PDF (16/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
Signal
TMS
TRST#
RESERVED[8:1]
NC[19:18], NC[16:1]
A_NC[10:1]
B_NC[10:1]
NC[17]
Total
I/O
Description
Test Mode Select: This signal controls the TAP controller state machine to
I
move to different states and is sampled on the rising edge of TCK.
If not utilizing JTAG, this signal can be left as a no connect.
Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN
I
logic.
If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down
resistor.
I
Reserved: (8 pins) These input pins should be pulled low
Use an approximately 8.2KΩ resistor to pull-down to ground.
O
No Connect: (39 pins) These output pins should be left floating
O
This signal requires an external pull-up, 8.2K ohm to 3.3V
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