NQ41210SL7JE Datasheet, PDF (33/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

Datasheet — 41210 Bridge
3.5.3 PCI and PCI-X Clock Specification
Clock measurement conditions are the same for PCI-X devices as for conventional PCI devices in a
3.3V signaling environment except for voltage levels specified in Table 26, “PCI and PCI-X Clock
Timings” on page 33. The same spread-spectrum clocking techniques are allowed in PCI-X as for
66 MHz conventional PCI. If a device includes a PLL, that PLL must track the input variations of
spread-spectrum clocking specified in Table 26.
Figure 7. PCI-X 3.3V Clock Waveform
Table 26.
PCI and PCI-X Clock Timings
Symbol Parameter
PCI-X 133
PCI-X 66
PCI 66
PCI 33
Min Max Min Max Min Max Min Max Units Notes
T_cyc
T_high
T_low
T_jit
—
fmod
fsprea
d
CLK Cycle
Time
CLK high
time
CLK low
time
CLK Period
Jitter
CLK slew
rate
Modulation
frequency
Frequency
spread
Average
Absolute
Minimum
7.5 20 15 20 15 30
7.375
14.8
14.8
3
6
6
3
6
6
125 -125 200 -200 200 -200
Slew Rate
1.5
4 1.5
4
1.5
4
Spread Spectrum Requirements
30
33 30
33
30
33
-1
0
-1
0
-1
0
30
29.7
11
11
300
1
∞
-300
4
ns
ns
ns
ns
ps
V/ns
kHz
%
1,3,4
1,3
5
2
1. For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and
jitter limits except while RSTIN# is asserted.
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the
PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter).
4. Average T_cyc is measured over any 1 µs period of time and must include all sources of clock variation.
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