NQ41210SL7JE Datasheet, PDF (13/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

Datasheet — 41210 Bridge
2.5
PCI Bus Interface Clocks and, Reset and Power
Management (Two Interfaces)
Table 5.
PCI Clock and Reset Pins
Signal
I/O
Description
A_CLKO[6:0]
B_CLKO[6:0]
PCI Clock Output: 33/66/100/133 MHz clock for a PCI device. X_CLK[6] must be connected to the
respective X_CLKIN input. for feeding the PCI interface logic. Unused clock outputs may be
disabled via the “Offset 43: PCLKC – PCI Clock Control” register and should be treated as no
O ^{connects on the board.}
Note: Registers are listed in the Intel® 41210 Serial to Parallel PCI Bridge
Developer’s Manual.
A_CLKIN
B_CLKIN
A_RST#
B_RST#
A_PME#
B_PME#
Total
I
PCI Clock In: This signal is PCI clock feedback input. This pin should be connected to the
corresponding X_CLKO[6] through a 22Ω±1% series resistor.
O PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus.
PCI Power Management Event: PCI bus power management event signal. This is a shared open
drain input from all the PCI cards on the corresponding PCI bus segment. This is a level sensitive
I _{signal that will be converted to a PME event on PCI Express.}
This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally.
20
2.6
Interrupt Interface (Two Interfaces)
This section lists the interrupt interface signals. There are two sets of interrupt signals for the
standard INTA:INTD pci signals.
Table 6.
Interrupt Interface Pins
Signal
I/O
Description
A_INTA#
A_INTB#
A_INTC#
A_INTD#
B_INTA#
B_INTB#
B_INTC#
B_INTD#
Total
Interrupt Request Bus: The interrupt lines from PCI interrupts INTA#:INTD# can be routed to these
interrupt lines.
I
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for more information on device
numbering.
8
2.7
Reset Straps
The following signals are used for static configuration. These signals are all sampled on the rising
edge of PERST#.
13