NQ41210SL7JE Datasheet, PDF (32/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
Table 25. PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)
T_on
Float to Active Delay
T_off
Active to Float Delay
T_su
Input Setup Time to CLK
0
7
1.2
0
7
1.7
ns
1, 6, 8
ns
1, 6, 8
ns
3, 7
T_h
Input Hold Time from CLK
0.5
T_rst
Reset Active Time after power
stable
1
T_rst-clk
Reset Active Time after CLK stable 100
T_rst-off
Reset Active to output float delay
40
T_rrsu
PxREQ64# to RSTIN# setup time 10
T_rrh
RSTIN# to PxREQ64# hold Time 0
50
T_rhfa
RSTIN# high to first configuration
access
2²⁶
T_rhff
RSTIN# high to first PxFRAME#
Assertion
5
T_pvrh
Power valid to RSTIN# high
100
T_prsu
PCI-X initialization pattern to
RSTIN# setup time
10
T_prh
RSTIN# to PCI-X initialization
pattern hold time
0
50
T_rlcx
Delay from RSTIN# low to CLK
frequency change
0
0.5
1
100
40
10
0
50
2²⁶
5
100
10
0
50
0
ns
3
ms
4
µs
4
ns
4
ns
ns
7
clocks
clocks
ms
clocks
ns
7
ns
1. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28.
2. Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a. Maximum times are measured with the test point and
load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
3. See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28 and the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a.
4. RST# is asserted and deasserted asynchronously with respect to CLK.
5. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time.
7. Maximum value is also limited by delay to the first transaction (T_rhfa). The PCI-X initialization pattern control
signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the first
PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.
8. Device must meet this specification independent of how many outputs switch simultaneously.
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