NQ41210SL7JE Datasheet, PDF (29/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

Datasheet — 41210 Bridge
3.5.1.2
Table 23.
4. Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both V_TX-D+
and V_TX-D-.
Differential Receiver (RX) AC Input Specifications
Table 23 defines the AC specifications of parameters for all differential Receivers (RXs). The
parameters are specified at the component pins.
Differential Receiver (RX) AC Input Specifications
Symbol
UI
T_RX-EYE
T_RX-EYE-
MEDIAN-to-
MAX-JITTER
T_RX-IDLE-DET-
DIFF-
ENTERTIME
L_RX-SKEW
Parameter
Min Nom Max Units
Comments
Unit Interval
399.88 400 400.12 ps
Minimum
Receiver Eye
0.4
Width
Maximum time
between the jitter
median and
maximum
deviation from
the median.
Unexpected
Electrical Idle
Enter Detect
Threshold
Integration Time
Total Skew
UI
0.3
UI
10
ms
20
ns
The UI is 400 ps +/-300 ppm. UI
does not account for SSC dictated
variations. See Note 1.
The maximum interconnect media
and transmitter jitter that can be
tolerated by the receiver can be
derived asT_{RX-MAX-JITTER} =1 -T_RX-
EYE ^{=0.6 UI}
See Notes 2 and 3.
Jitter is defined as the
measurement variation of the
crossing points (V_{RX- DIFFp-p} = 0 V)
in relation to an appropriate
average TX UI.
See Notes 2 and 3.
An unexpected electrical idle (V_RX-
DIFFp-p ^<VRX-IDLE-DET- DIFFp-p^{) must}
be recognized no longer than T_RX-
IDLE-DET- DIFF-ENTERTIME ^{to signal}
an unexpected idle condition.
Across all Lanes on a port. This
includes variation in the length of a
skip ordered-set (e.g., COM and 1
to 5 SKP symbols) at the RX as well
as any delay differences arising
from the interconnect itself.
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
“Compliance Test/Measurement Load” on page 23 should be used as the RX device when taking
measurements (also refer to the Receiver Compliance Eye Diagram as shown in Figure 3, “Minimum
Receiver Eye Timing and Voltage Compliance Specification” on page 23). If the clocks to the RX and TX are
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
3. A T_RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the
transmitter and interconnect collected any 250 consecutive UIs. The T_{RX-EYE-MEDIAN-to-MAX-JITTER}
specification ensures a jitter distribution in which the median and the maximum deviation from the median is
less than half of the total .6 UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that
the median is not the same as the mean. The jitter median describes the point in time where the number of
jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the
RX and TX are not derived from the same clock chip, the appropriate average TX UI must be used as the
reference for the eye diagram.
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