NQ41210SL7JE Datasheet, PDF (14/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
Table 7.
Reset Strap Pins
Signal
A_133EN
B_133EN
A_STRAP[6:0
]
B_STRAP[6:0
]
A_TEST[2:1]
B_TEST{2:1]
CFGRETRY
Total
I/O
Description
PCI-X 133 MHz Enable: This pin, when high, allows the PCI-X segment to
run at 133 MHz when X_PCIXCAP is sampled high. When low, the PCI-X
I
segment will only run at 100 MHz when X_PCIXCAP is sampled high.
Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to
ground.
Internal Test Modes: Straps 6, 2:0 should be pulled low and straps 5:3
must be pulled high for normal operation.
X_STRAP Logic Level
0
‘0’
1
‘0’
I
2
‘0’
3
‘1’
4
‘1’
5
‘1’
6
‘0’
Use approximately an 8.2KΩ resistor to pull-up to VCC33 or pull-down to
VSS
Internal Test Modes: These straps should be pulled high to VCC33.
I
Use approximately an 8.2KΩ resistor to pull-up to VCC33.
Configuration Retry: This pin, when sampled high sets the Configuration
Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC.
I
If no local initialization is needed, this pin should be pulled low to VSS.
Refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide for
more information.
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