NQ41210SL7JE Datasheet, PDF (10/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

41210 Bridge — Datasheet
2.2
Table 2.
PCI Express Interface
PCI Express Interface Pins
Signal
REFCLKp/
REFCLKn
PETp[7:0]/
PETn[7:0]
PERp[7:0]/
PERn[7:0]
PE_RCOMP[1:0]
Total
I/O
Description
PCI Express Reference Clocks: 100 MHz differential clock pair.
I
PCI Express Serial Data Transmit: PCI Express differential data transmit
signals.
O
X8 Mode: All PETp[7:0]/ PETn[7:0] are used
X4 Mode: Only PETp[3:0]/ PETn[3:0] are used
x1 Mode: Either PETp[0]/ PETn[0] is used or PETp[7]/ PETn[7] is used
PCI Express Serial Data Receive: PCI Express differential data receive
signals.
I
X8 Mode: All PERp[7:0]/ PERn[7:0] are used
X4 Mode: Only PERp[3:0]/ PERn[3:0] are used
x1 Mode: Either PERp[0]/ PERn[0] is used or PERp[7]/ PERn[7] is used
PCI Express Compensation Inputs: Analog signals. Connect to a
I
24.9Ω±1% pull-up resitor to 1.5V. A single resistor can be used for both
signals.
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2.3
PCI Bus Interface (Two Instances)
Each interface is marked by either the letter “A” or “B” to signify the interface. Therefore, A_AD
refers to the AD bus on PCI bus A, and B_AD refers to the AD bus on PCI bus B. For pin names
described in the following sections, an ‘X’ in the name indicates either A or B, for the PCI bus A
and PCI bus B sides. For example, X_PAR signal would be called A_PAR on the PCI bus A and
B_PAR on the PCI bus B.
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