NQ41210SL7JE Datasheet, PDF (35/52 Pages) Intel Corporation – Intel® 41210 Serial to Parallel PCI Bridge

Datasheet — 41210 Bridge
3.5.4
Table 27.
41210 Bridge Clock Timings
41210 Bridge Clock Timings
Symbol
Parameter
Min
Max
CLK100
T_period
T_rise
T_fall
—
—
T_ccjitter
—
—
—
—
—
CLK133
Average Period
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
Cross point at 1 V
Cycle to Cycle jitter
Duty Cycle
Maximum voltage allowed at input
Minimum voltage allowed at input
Rising edge ringback
Falling edge ring back
10.0
10.2
300
600
300
600
20%
0.51
0.76
200
45
55
1.45
-200
0.85
0.35
T_period
T_rise
T_fall
—
—
T_ccjitter
—
—
—
—
—
CLK33
Average Period
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
Cross point at 1V
Cycle to Cycle jitter
Duty Cycle
Maximum voltage allowed at input
Minimum voltage allowed at input
Rising edge ringback
Falling edge ring back
7.5
7.65
300
600
300
600
20%
0.51
0.76
125
45
55
1.45
-200
0.85
0.35
T_period
T_high
T_low
—
—
T_rise
T_fall
CLK period
CLK high time
CLK low time
Rising edge rate
Falling edge rate
CLK rise time
CLK fall time
30.0
N/A
12.0
N/A
12.0
N/A
1.0
4.0
1.0
4.0
0.5
2.0
0.5
2.0
1. Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.
Units
Notes
ns
6
ps
7,8
ps
7,8
7,9
V
ps
%
V
mV
V
V
ns 6
ps 7,8
ps 7,8
7,9
V
ps 10
%
V
mV
V
V
ns 1,2
ns 3
ns 4
V/ns 5
V/ns 5
ns 5
ns 5
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