BX80547PG3200FSL8Q6 Datasheet, PDF (32/105 Pages) Intel Corporation – Intel® Pentium® 4 Processor 6xxΔ Sequence and Intel® Pentium® 4 Processor Extreme Edition

Electrical Specifications
.
Table 2-13. PWRGOOD and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit Notes^{1, 2}
V_HYS Input Hysteresis
200
350
mV
3
V_T+
Input low to high threshold
voltage
0.5 * (V_TT + V_{HYS_MIN})
0.5 * (V_TT + V_{HYS_MAX})
V
4
V_T-
Input high to low threshold
voltage
0.5 * (V_TT – V_{HYS_MAX})
0.5 * (V_TT – V_{HYS_MIN})
V
4
V_OH Output High Voltage
N/A
I_OL Output Low Current
—
I_LI Input Leakage Current
—
V_TT
45
± 200
V
4
mA
5
µA
6
I_LO Output Leakage Current
—
± 200
µA
—
R_ON Buffer On Resistance
7
12
Ω
—
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open drain.
3. V_HYS represents the amount of hysteresis, nominally centered about 0.5 * V_TT, for all TAP inputs.
4. The V_TT referred to in these specifications refers to instantaneous V_TT.
5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test
load.
6. Leakage to V_SS with land held at V_TT.
Table 2-14. VTTPWRGD DC Specifications
Symbol
V_IL
V_IH
Parameter
Input Low Voltage
Input High Voltage
Min
Typ
Max Unit
—
—
0.3
V
0.9
—
—
V
Notes
Table 2-15. BSEL [2:0] and VID[5:0] DC Specifications
Symbol
Parameter
Max
R_ON (BSEL) Buffer On Resistance
60
R_ON (VID) Buffer On Resistance
60
I_OL
Max Land Current
8
I_LO
Output Leakage Current
200
V_TOL
Voltage Tolerance
V_TT (max)
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to V_SS with land held at 2.5 V.
Unit
Ω
Ω
mA
µA
V
Notes^{1, 2}
—
—
—
3
—
Table 2-16. BOOTSELECT DC Specifications
Symbol
Parameter
Min
Typ
Max
Unit
V_IL
Input Low Voltage
—
—
0.24
V
V_IH
Input High Voltage
0.96
—
—
V
NOTES:
1. These parameters are not tested and are based on design simulations.
Notes
1
—
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