BX80547PG3200FSL8Q6 Datasheet, PDF (15/105 Pages) Intel Corporation – Intel® Pentium® 4 Processor 6xxΔ Sequence and Intel® Pentium® 4 Processor Extreme Edition

Electrical Specifications
2 Electrical Specifications
2.1
2.2
2.3
This chapter describes the electrical characteristics of the processor interfaces and signals. DC
electrical characteristics are provided.
FSB and GTLREF
Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology.
Platforms implement a termination voltage level for GTL+ signals defined as V_TT. V_TT must be
provided via a separate voltage source and not be connected to V_CC. This configuration allows for
improved noise tolerance as processor frequency increases. Because of the speed improvements to
the data and address bus, signal integrity and platform design methods have become more critical
than with previous processor families. Contact your Intel representative for further details and
documentation.
The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine
if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (see
Table 2-18 for GTLREF specifications). Termination resistors are provided on the processor silicon
and are terminated to V_TT. Intel chipsets will also provide on-die termination, thus eliminating the
need to terminate the bus on the system board for most GTL+ signals.
Some GTL+ signals do not include on-die termination and must be terminated on the system board.
See Table 2-4 for details regarding these signals.
The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+
signals are based on flight time, rather than capacitive deratings. Analog signal simulation of the
FSB, including trace lengths, is highly recommended when designing a system.
Power and Ground Lands
For clean on-chip power distribution, the Pentium 4 processor has 226 VCC (power), 24 VTT, and
273 VSS (ground) lands. All power lands must be connected to V_CC, all VTT lands must be
connected to V_TT, and all VSS lands must be connected to a system ground plane. The processor
VCC lands must be supplied by the voltage determined by the Voltage IDentification (VID)
signals.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of
generating large current swings between low and full power states. This may cause voltages on
power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime
of the component. For further information and design guidelines, refer to the Voltage Regulator
Down (VRD) 10.1 Design Guide for Desktop LGA775 Socket. Contact your Intel representative for
further details and documentation.
Datasheet
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