English
Language : 

TC1765 Datasheet, PDF (9/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller
Preliminary
Pin Configuration
TC1765
1
2
A
AN AN
17 16
B
AN
19
AN
18
C
V AREF1
AN
20
D
V SSA1
AN
23
3
4
5
AN
8
VSSM
AN
7
AN
11
V DDM
AN
5
6
7
8
9
10 11 12 13 14 15 16 17 18
AN
4
AN
0
V AREF0 V DDA0 P 0.0
P 0 .4
P 0 .5
P0.8 P0.10 P 0.14 P5.4
P4.2 P3.11 A
AN
2
V SSA0 P0.2
P 0 .7
P 0.9 P0.15 V DDP
P 5 .1
P 5 .2
P4.3 P3.15 P3.14 P3.10 B
AN
10
AN
9
AN
6
V AGND0 P0.3
V DDP P 0.11 P 0.12 P 5.3
P 4 .7
P4.1 P3.12 P4.6
P 4 .4
P 3 .9
P 3 .8
C
AN
12
AN
13
AN
3
AN
1
P0.1 P0.6
V SS P 0.13 V DD P 5.0 P 4.5 P 4.0 P 3.13 V DDP P 3.7 P 3.6 D
E
D29 VAGND1
AN
15
AN
14
P3.4 P3.3 P3.5 P3.2 E
F D28 D30
AN
22
AN
21
G D27 D26 VDD VDDA1
RAM
TP.0 TP.1 V SS V SS TP.14 TP.15
P 3.1 P 3.0 V DD P 2.15 F
P 2.12 P2.14 P2.13 P2.10 G
H D23 D22 D25 D31
TP.2 TP.3 V SS V SS TP.12 TP.13
P 2.11 P2.9 V DDP P2.4 H
J D20 D21 VDD D24
VSS VSS VSS VSS VSS VSS
P2.8 P2.5 P2.3 P2.0 J
K D17 D18 D19 VSS
VSS VSS VSS VSS VSS VSS
V SS P 1.15 P 1.12 P 1.13 K
L D16 VDD D14 D10
TP.4 TP.5 V SS V SS TP.10 TP.11
P 1.14 P 1.11 V DDP P 1.7 L
M D15 D13 D11 D8
TP .6 TP .7 V SS V SS TP .8 TP .9
P2.7 P1.10 P1.3 P1.6 M
N
EC
IN
D12
D9
D6
P
EC
OUT
VDD
D7
D2
R D4
D3
D5
D1
W AIT/
IN D
A3
T RD
RD/
WR
D0
VDD
A0
A6
U ADV BC0 BC2 BAA A2 A7
V BC1 BC3 CODE A1 A4 A9
1
2
3
4
5
6
P 2 .2
P 1 .4
BY
PASS
P 1 .0
N
P 1 .5
P 1 .8
V DD
SBRAM
HD
RST
P
A5
A8
A19
CS3
OCD
SE
TDO
CPU
CLK
TRST
P 1 .2
P 1 .1
VSS
OSC
VDD R
OSC
A11
A15
A16
CS2
A21 BRK TCK
OUT
TDI
P 2 .1
P 2 .6
PO
RST
XTAL
2
T
A10
A14
A18
A23
VDD
CS0
VDD
A13
BRK
IN
P 1 .9
NMI
XTAL
1
U
V DD
A12
V DD
A22
CSEMU/
CSOVL
CS1
A20
A17
TMS
TEST
MODE
N.C .
N .C . V
7
8
9
10 11 12 13 14 15 16 17 18
The Trace port is only available in the TC 1765T.
M C P05009
Figure 3 TC1765 Pinning for P-LBGA-260 Package (top view)
Data Sheet
5
V1.2, 2002-12