TC1765 Datasheet, PDF (25/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
High-Speed Synchronous Serial Interfaces
Figure 6 shows a global view of the functional blocks of the two High-Speed
Synchronous Serial interfaces SSC0 and SSC1.
Clock
C o n tro l
f_SSC0
A d d re s s
Decoder
E IR
Interrupt TIR
Control _RIR
To DMA
SSC0
M o d ule
(Kernel)
RXD
TXD
RXD
TXD
Slave
M a ste r
Port 0
C o n tro l
P0.11 /
MTSR0
P0.10 /
MRST0
P0.9 /
SCLK0
Clock
C o n tro l
f_SSC1
A d d re s s
Decoder
E IR
Interrupt ^TIR
Control _RIR
To DMA
SSC1
M o d ule
(Kernel)
RXD
TXD
RXD
TXD
Slave
M a ste r
Port 5
C o n tro l
P5.4 /
MTSR1
P5.3 /
MRST1
P5.2 /
SCLK1
MCB05051
Figure 6 General Block Diagram of the SSC Interfaces
Each of the SSC modules has three I/O lines, located at Port 0 and Port 5. Each of the
SSC modules is further supplied by separate clock control, interrupt control, address
decoding, and port control logic.
The SSC supports full-duplex and half-duplex serial synchronous communication up to
20 Mbit/s (@ 40 MHz module clock) with receive and transmit FIFO support. The serial
clock signal can be generated by the SSC itself (master mode) or can be received from
an external master (slave mode). Data width, shift direction, clock polarity, and phase are
programmable. This allows communication with SPI-compatible devices. Transmission
Data Sheet
21
V1.2, 2002-12