TC1765 Datasheet, PDF (55/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
PLL Operation
The f_VCO clock of the PLL has a frequency which is a multiple of the externally applied
clock f_OSC. The factor for this is controlled through the fix divider value N (N = 10) applied
to the divider in the feedback path. The K-Divider is defined by bit field KDIV. Table 6
lists the possible values for KDIV and the resulting division factor.
The VCO output frequency and the resulting system clock is determined by:
f_VCO = 10 × f_OSC
f_SYS
=
f_VCO
/
K
=
10
K
×
f_OSC
Table 6
Output Frequencies f_SYS Derived from Various Output Factors
K-Factor
Selected
Factor
KDIV
2
000_B
4
010_B
5²⁾
011_B
6
100_B
8
101_B
9²⁾
110_B
10
111_B
16
001_B
f_VCO =
150 MHz
75¹⁾
37.5
30
24.5
18.75
16.67
15
9.38
f_SYS
f_VCO =
160 MHz
80¹⁾
40
32
26.67
20
17.78
16
10
f_VCO =
200 MHz
100¹⁾
50¹⁾
40
33.33
25
22.22
20
12.5
Duty
Cycle
[%]
50
50
40
50
50
44
50
50
1) _{These combinations cannot be used because the maximum system clock of 40 MHz is exceeded.}
2) _{These odd K-Factors should not be used (not tested because of the unsymmetrical duty cycle).}
Data Sheet
51
V1.2, 2002-12