TC1765 Datasheet, PDF (18/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
Table 1
Symbol
TDO
TMS⁸⁾
OCDSE⁸⁾
BRKIN⁸⁾
BRKOUT
NMI⁸⁾
HDRST⁸⁾
PORST
BYPASS
Pin Definitions and Functions (cont’d)
Pin In Functions
Out
R12 O JTAG Module Serial Data Output³⁾
V15 I JTAG Module State Machine Control Input
R11 I
OCDS Enable Input
A low level on this pin during power-on reset (PORST = 0)
enables the on-chip debug support (OCDS). In addition, the
level of this pin during power-on reset determines the boot
configuration.
U15 I
T12 O
OCDS Break Input
A low level on this pin causes a break in the chip’s execution
when the OCDS is enabled. In addition, the level of this pin
during power-on reset determines the boot configuration.
OCDS Break Output³⁾
A low level on this pin indicates that a programmable OCDS
event has occurred.
U17 I Non-Maskable Interrupt Input
A high-to-low transition on this pin causes an NMI-Trap
request to the CPU.
P18 I/O Hardware Reset Input / Reset Indication Output⁶⁾
Assertion of this open-drain bidirectional pin causes a
synchronous reset of the chip through external circuitry.
The internal reset circuitry drives this pin in response to a
power-on, hardware, watchdog and power-down wake-up
reset for a specific period of time. For a software reset, it is
programmable whether this pin is activated or not.
T17 I
Power-on Reset Input
A low level on PORST causes an asynchronous reset of the
entire chip. During power-up of the TC1765, this pin must be
held active (low).
N17 I
PLL Bypass Control Input
This pin is sampled during power-on reset (PORST = 0). If
BYPASS is at high level, direct drive mode operation of the
clock circuitry is selected and the PLL is bypassed.
Data Sheet
14
V1.2, 2002-12