TC1765 Datasheet, PDF (27/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
TwinCAN Interface
Figure 7 shows a global view of the functional blocks of the TwinCAN module.
C lo c k
f_CAN
C o n tro l
Address
Decoder
SR0
SR1
SR2
SR3
Interrupt
C o n tro l
SR4
SR5
SR6
SR7
Tw inCAN M odule Kernel
B its tre a m
Processor
Message
B u ffe rs
Interrupt
C o n tro l
Tim ing
C o n tro l
Error
H a n d lin g
C o n tro l
TXDC0
RXDC0
TXDC1
Port
C o n tro l
RXDC1
P0.13 /
TXDCAN0
P0.12 /
RXDCAN0
P0.15 /
TXDCAN1
P0.14 /
RXDCAN1
MCB05059
Figure 7 General Block Diagram of the TwinCAN Module
The TwinCAN module has four I/O lines located at Port 0. The TwinCAN module is
further supplied by a clock control, interrupt control, address decoding, and port control
logic.
The TwinCAN module contains two Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames are handled in accordance to CAN specification V2.0 part B (active).
Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit
identifiers as well as with extended frames with 29-bit identifiers.
Both CAN nodes share the TwinCAN module’s resources to optimize the CAN bus traffic
handling and to minimize the CPU load. The flexible combination of Full-CAN
functionality and the FIFO architecture reduces the efforts to fulfill the real-time
requirements of complex embedded control applications. Improved CAN bus monitoring
functionality as well as the increased number of message objects permit precise and
convenient CAN bus traffic handling.
Depending on the application, each of the thirty-two message objects can be individually
assigned to one of the two CAN nodes. Gateway functionality allows automatic data
exchange between two separate CAN bus systems, which decreases CPU load and
improves the real time behavior of the entire system.
Data Sheet
23
V1.2, 2002-12