TC1765 Datasheet, PDF (78/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
PLL Parameters
Note: All PLL characteristics defined on this and the next page are guaranteed by design
characterization.
V_SS = 0 V; V_DD = 2.30 to 2.75 V; T_A = -40 °C to +125 °C;
Parameter
Accumulated jitter
VCO frequency range
PLL base frequency
PLL lock-in time
Symbol
D_N
f_VCO
f_PLLBASE
t_L
Limit Values
min.
max.
see Figure 29
150
200
40
130
–
200
Unit
–
MHz
MHz
µs
Phase Locked Loop Operation
When PLL operation is enabled and configured (see Figure 16 and Page 51), the PLL
clock f_VCO (and with it the system clock f_SYS) is constantly adjusted to the selected
frequency. The relation between f_VCO and f_SYS is defined by: f_VCO = K × f_SYS. The PLL
causes a jitter of f_SYS and CPUCLK/ECOUT, which is directly derived from f_SYS and
which has its frequency.
The following two formulas define the (absolute) approximate maximum value of jitter D_N
in ns dependent on the K-factor, the system clock frequency f_SYS in MHz, and the
number P of consecutive f_SYS periods.
for P < ^23.5
K
D_N [ns] = ±
3.9
f_SYS [MHz]
×
P
+ 1.2
[1]
for P > ^23.5
K
91.7
D_N [ns] = ± _{fSYS [MHz] × K} + 1.2
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a value
of P that is defined by the K-factor of the PLL. Beyond this value of P the maximum
accumulated jitter remains at a constant value. Further, a lower system clock frequency
f_SYS results in a higher maximum jitter.
Figure 29 gives an example for typical jitter curves with K = 4 @40 MHz,
K = 6 @33 MHz, and K = 8@20/25 MHz.
Data Sheet
74
V1.2, 2002-12