TC1765 Datasheet, PDF (86/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
SSC Master Mode Timing
V_SS = 0 V; V_DDP = 4.5 to 5.25 V; T_A = -40 °C to +125 °C; C_L = 50 pF;
Parameter
Symbol
Limit Values
Unit
min.
max.
SCLK / MTSR low/high from ECOUT ¹⁾ t₆₀ CC –
7
ns
MRST setup to SLCK rising/falling edge t₆₁ SR 18²⁾
–
ns
MRST hold from SLCK rising/falling edge t₆₂ SR 10²⁾
–
ns
1) _{This parameter is valid for high current mode output driver characteristic and normal timing edge characteristic}
(POCON.PECx = 0 and POCON.PDCx = 0) of the corresponding SSC output lines.
2) _{Guaranteed by design characterization.}
t_ECOUT
ECOUT
t₆₀
t₆₀
t₆₀
SCLK
MTSR
State n-1
State n
State n+1
t₆₁
t₆₂
MRST
Data Valid
MCT05234
Note: The timing diagram assumes the highest possible baudrate operation.
(f_SSC = f_ECOUT, SSCx_CLC.RMC = 1, SSCx_BR.BR_VALUE = 0000_H)
Figure 35 SSC Master Mode Timing
Data Sheet
82
V1.2, 2002-12