TC1765 Datasheet, PDF (54/88 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1765
Preliminary
Clock Generation Unit
The Clock Generation Unit (CGU) in the TC1765, shown in Figure 16, consists of an
oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency
external clock signal to a high-speed internal clock for maximum performance. The PLL
also has fail-safe logic that detects degenerate external clock behavior such as abnormal
frequency deviations or a total loss of the external clock. It can execute emergency
actions if it looses its lock on the external clock.
In general, the CGU is controlled through the System Control Unit (SCU) module of the
TC1765.
XTAL1
Clock Generation Unit
CGU
O scillator ^fOSC
&
C irc u it
XTAL2
Phase
D e te c t.
VCO
N
D iv id e r
PLL
f_VCO
K
D iv id e r
1
MUX
0
S yste m _
CLK
f_SYS
Lock
D e te cto r
BYPASS
Figure 16
OSC_OK
Deep
Sleep
System Control Unit
SCU
LOCK KDIV PLLBYP
Register PLL_CLC
MCA04974
Clock Generation Unit Block Diagram
Data Sheet
50
V1.2, 2002-12