TDA5150 Datasheet, PDF (84/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
ADDR 0x1F
TDA 5150 Functional Description
ANTTDCC—Antenna Tuning and Duty Cycle
Configurations
Bit 7
reserved
w/0
Bit 6
DCC
DISABLE
w/0
Bit 5
Bit 4
DCCCONF DCCCONF
w/1
w/0
Bit 3
TUNETOP
w/0
Bit 2
TUNETOP
w/0
Bit 1
TUNETOP
w/0
Bit 0
TUNETOP
w/0
Bit 7 reserved
Bit 6 DCCDISABLE
Bit <5:4> DCCCONF
Bit 3:0 TUNETOP
Reserved, set to 0
Duty cycle control disable
Duty cycle control delay configuration bit <1:0>
Antenna tuning top (PAOUT pin) bit <3:0>
DCCDISABLE
DCCCONF
TUNETOP
ADDR 0x20
Duty cycle control disable (must be 0 for ISMB=0)
0 enabled
1 disabled (delay = 0ps)
Duty cycle control delay configuration (ISMB = 1/2/3, for ISMB = 0 => delay = 0 ps)
00: 43%
(69/35/33
ps)
01: 39% 10: 35%
(207/104/9 (346/173/
8 ps)
164 ps)
11: 31%
(484/242/
230 ps)
Antenna tuning top capacitor selection (4-bits):
Individual switch of
capacitor banks
0:
switched off
1:
switched on
Bit(0) ==> Bit(1) ==> Bit(2) ==> Bit(3) ==>
60 fF
120 fF
240 fF
480 fF
RES1—Reserved
Bit 7
n.u.
/
Bit 6
reserved
w/1
Bit 5
reserved
w/0
Bit 4
reserved
w/0
Bit 3
reserved
w/1
Bit 2
reserved
w/1
Bit 1
reserved
w/0
Bit 0
reserved
w/0
Bit <7:0>
reserved
Reserved, set bits <6,3,2> to 1 and bits <5, 4, 1, 0> to 0
Data Sheet
84
V 1.0, July 2009