TDA5150 Datasheet, PDF (35/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
TDA 5150 Functional Description
2.4.5.3 SFRs related to Crystal Oscillator and Clock Divide
r
ADDR 0x06
CLKOUTCFG - Clock Pre- and Post-scaler
Bit 7
CLKSRC
w/0
Bit 6
CLKSRC
w/0
Bit 5
Bit 4
AFTERSCAlE AFTERSCALE
w/0
w/0
Bit 3
PRESCALE
w/1
Bit 2
PRESCALE
w/0
Bit 1
PRESCALE
w/0
Bit 0
CLKOUTENA
w/1
Bit <7:6> CLKSRC
Bit <5:4> AFTERSCALE
Bit <3:1> PRESCALE
Bit 0 CLKOUTENA
Clock source selection bit <1:0>
00: after prescaler, 01: after BRDIV counter
10: after BRDIV counter inverted, 11: after afterscaler
Afterscaler selection bit <1:0>
divide by 2^AFTERSCALE
Prescaler selection bit <2:0>
divide by 2^PRESCALE
0 if CLKOUT disabled. In this case CLKOUT goes
High after crystal oscillator achieves stable level
1 if clock output enabled
ADDR 0x07
BDRDIV—Bit-rate Divider
Bit 7
BDRDIV
w/1
Bit 6
BDRDIV
w/0
Bit 5
BDRDIV
w/0
Bit 4
BDRDIV
w/0
Bit 3
BDRDIV
w/0
Bit 2
BDRDIV
w/0
Bit 1
BDRDIV
w/0
Bit 0
BDRDIV
w/0
Bit <7:0> BDRDIV
BDRDIV divider bit <7:0>
2.4.6 Sigma-Delta fractional-N PLL Block
The Sigma-Delta fractional-N PLL contained on-chip is the core piece of the
transmitter.
The advantage of a fractional-N PLL is that not only integer multiples of the crystal
frequencies [N * fXTAL] can be generated, but also values of N-multiples plus a fractional
part.
Part of the PLL is a VCO (Voltage Controlled Oscillator) running at a center frequency of
approximately 1.8 GHz. The VCO frequency is divided at first by 2 in a prescaler block
with fixed division ratio. It is then further divided by 1, 2 or 3 in the band select divider
block, the resulting frequency equaling the transmitter’s RF output frequency.
Data Sheet
35
V 1.0, July 2009