TDA5150 Datasheet, PDF (26/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
TDA 5150 Functional Description
2.4.3.5 Timing Diagrams
In the following timing diagrams the 4 possible SPI commands are shown. The examples
are valid for the case of SCK is low when EN line goes from Low into High (rising edge).
Therefore the incoming SDIO data is sampled at the falling edge of SCK, and data is
output on SDIO line by the rising edge of SCK signal.
WRITE SFR:
EN
SCK
SDIO
7
07
0
Command
Address
Data Byte
0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
READ SFR:
EN
SCK
SDIO
7
07
0
Command
Address
Data Byte
0 1 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
BURST write SFR:
EN
SCK
SDIO
7
07
07
0
Command
Address
Data Byte 0
Data Byte 1
0 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
7
0
Data Byte N
D7 D6 D5 D4 D3 D2 D1 D0
TRANSMIT data:
EN
SCK
> 1000us if TX issued from STDBY
else determined by SCK speed
> 100us
7
0
Command
Configuration
Data to transmit
SDIO
1 1 ABCD EF
d1
d2
d3
d4
d5
Figure 9 Timing Diagrams of 3-wire SPI
Data Sheet
26
V 1.0, July 2009