TDA5150 Datasheet, PDF (36/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
TDA 5150 Functional Description
This RF signal is then further divided in a multimodulus divider block down to a frequency
which is in same range as those of the reference signal’s, input from the reference
oscillator (i.e the crystal oscillator).
The reference oscillator’s frequency and the VCO’s subdivided frequency, input from
multimodulus divider are compared in a phase detector. On the output of the phase
detector an error signal, proportional to the phase difference of the two, above
mentioned signals is obtained. The phase-error signal is converted to a bipolar current
by the charge pump and then fed into the loop filter (integrator).
The output of this integrator controls the VCO frequency via the tuning voltage and so
closing the loop.
The multimodulus divider is able to switch between different dividing factors. Thus it is
possible e.g. to divide by 2.5 by first dividing by 2, than by 3, followed by 2 again, and so
on. The dividing factor is defined by the Sigma-Delta Modulator.
2.4.6.1 Fractional Spurs
Due to the behavior of Sigma-Delta PLLs, spurs are generated at frequencies close to
the integer multiples of the reference frequency. These spurs are named Fractional
Spurs. It is therefore recommended to use PLL division ratios (output RF frequency
divided by crystal oscillator frequency) with fractional parts between 0.1 and 0.9, or in
other words, the crystal frequency should be chosen in such way to yield for fractional
part of the PLL division ratio values between 0.1 and 0.9.
2.4.6.2 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator runs at approximately 1.8 GHz. This is 2, 4, or 6 times
the desired RF output frequency, dependent on the frequency band settings.
To trim out production tolerances of the VCO, a VCO Auto Calibration mechanism (VAC)
is implemented and runs automatically during each start up of the PLL. First a fixed,
internal voltage is applied to the VCO, and the generated RF frequency is divided by 4
(or 8 for 868/915 MHz bands). The positive transitions are then counted during 32
system clock cycles. The result is compared to a configured number, derived from the
desired RF frequency value (as the formula shows). The VCO is then automatically fine-
tuned, before an RF transmission starts.
PLLINT<6:0> + -^P----^L---^L----^F----^R-----^A----^C----^<----²---⁰---^:--⁰---^>----⁺----⁰---^.--⁵-
V A C _CTR <8:0>
=
-----------------------------------------------------------------²---²--¹----^–----⁰---^.--⁵--------------------
(ISMB<1> + 1) × 4
× VAC_NXOSC<5:0>
where:
• VAC_CTR<8:0> has to be calculated according the formula above. It contains the
optimal number of positive transitions to which the VAC-counter result is compared.
Data Sheet
36
V 1.0, July 2009