TDA5150 Datasheet, PDF (52/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
ADDR 0x1F
TDA 5150 Functional Description
ANTTDCC—Antenna Tuning and Duty Cycle
Configurations
Bit 7
reserved
w/0
Bit 6
DCC
DISABLE
w/0
Bit 5
Bit 4
Bit 3
DCCCONF DCCCONF TUNETOP
w/1
w/0
w/0
Bit 2
TUNETOP
w/0
Bit 1
TUNETOP
w/0
Bit 0
TUNETOP
w/0
Bit 7 reserved
Bit 6 DCCDISABLE
Bit <5:4> DCCCONF
Bit 3:0 TUNETOP
Always use 0
Duty cycle control disable
Duty cycle control delay configuration bit <1:0>
Antenna tuning top capacitor bit <3:0>
DCCDISABLE
DCCCONF
TUNETOP
Duty cycle control disable (must be 0 for ISMB=0)
0 enabled
1 disabled (delay = 0ps)
Duty cycle control delay configuration (ISMB = 1/2/3, for ISMB = 0 => delay = 0 ps)
00: 43%
(69/35/33
ps)
01: 39% 10: 35%
(207/104/9 (346/173/
8 ps)
164 ps)
11: 31%
(484/242/
230 ps)
Antenna tuning top capacitor selection (4-bits):
Individual switch of
capacitor banks
0:
switched off
1:
switched on
Bit(0) ==> Bit(1) ==> Bit(2) ==> Bit(3) ==>
60 fF
120 fF
240 fF
480 fF
2.4.9 Operating Modes
TDA 5150 has 3 main operating modes: SLEEP, STANDBY, TRANSMIT
and 2 temporary modes: XOSC_ENABLE and PLL_ENABLE.
2.4.9.1 SLEEP Mode
SLEEP is the lowest power consumption mode. Most of the internal blocks, excepting
the SPI interface are powered down and consequently the content of SFRs is going lost.
Therefore the SFR bank requires a full reprogramming after exiting SLEEP mode.
The SPI interface stays active and is supplied via the Low Power Voltage Regulator
while in SLEEP mode.
The SPI interface is able to detect bus non-idle conditions and it will wake up the
transmitter if the EN pin is taken high and at least 3 pulses are applied to SCK pin.
Data Sheet
52
V 1.0, July 2009