TDA5150 Datasheet, PDF (22/106 Pages) Infineon Technologies AG – On-chip, high resolution fractional-N synthesizer and Sigma-Delta modulator with ASK, FSK, GFSK options

TDA 5150
TDA 5150 Functional Description
• SCK - clock input pin with embedded pull-down resistor. If SCK is at low level
while EN goes high, the incoming SDIO data is sampled by falling edge of the SCK
and the output SDIO data is set by the rising edge of SCK. Contrariwise, If SCK is at
high level when EN goes high, the SDIO data is sampled with the rising edge of the
SCK clock and output on SDIO by falling edge of the SCK clock. For details refer to
Figure 6 and Figure 7.
SPI commands are started by the rising edge on the EN line and terminated by the falling
edge on EN.
The available Burst Write mode allows configuration of several SFRs within one block
access, without cycling the EN line Low - High - Low for each individual byte. By keeping
the EN line at High level, subsequent bytes could be sent, and the byte address counter
is autoincremented, thus speeding up the transfer on the SPI bus.
A self-explaining diagram is found here: Chapter 9 Timing Diagrams of 3-wire SPI.
The active edge of SCK (during SPI commands) is programmable, and it is determined
by the level on SCK line at the moment of activation of the EN line (rising edge on EN).
If SCK is low at that moment, the incoming SDIO data will be sampled with the falling
edge of SCK, and output by rising edge of SCK (see Figure 6 below)..
t_DS
EN
SCK
SDIO
SCK level sampled
tEN
t_SSu
tCH
tSHo
tNEN
Output
Sample
t_CL
(write SDIO)
(read SDIO)
tIDSu t_IDHo
Figure 6 SPI Timing — SCK low at rising edge of EN
If SCK is high during occurrence of rising edge on EN, incoming SDIO data is sampled
with the rising edge on SCK, and output by falling edge of SCK, as illustrated in Figure 7.
Data Sheet
22
V 1.0, July 2009