XC161CJ_02 Datasheet, PDF (73/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

Preliminary
tp_D
tp_E
CLKOUT
tc₁₄
RD, WR
XC161
Derivatives
Timing Parameters
tp_RDY
tp_F
tc₁₁
D15-D0
(read)
D15-D0
(write)
READY
Synchronous
READY
Asynchron.
tc₁₉
tc₂₀
Data In
tc₂₁
Data Out
tc₁₉ tc₂₀ tc₁₉ tc₂₀
Not Rdy Ready
tc₁₉ tc₂₀ tc₁₉ tc₂₀
Not Rdy Ready
Figure 20 READY Timing
Note: If the READY input is sampled inactive at the indicated sampling point (“Not Rdy”)
a READY-controlled waitstate is inserted (tp_RDY),
sampling the READY input active at the indicated sampling point (“Ready”)
terminates the currently running bus cycle.
Note the different sampling points for synchronous and asynchronous READY.
This example uses one mandatory waitstate (see tp_E) before the READY input is
evaluated.
Data Sheet
69
V1.0, 2002-03