XC161CJ_02 Datasheet, PDF (10/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
General Device Information
Table 2
Pin Definitions and Functions
Symbol Pin Input Function
Num. Outp.
P20.12 3
IO
For details, please refer to the description of P20.
NMI 4
I
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the XC161 into power down
mode. If NMI is high, when PWRDN is executed, the part will
continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
P6
P6.0 7
P6.1 8
P6.2 9
P6.3 10
P6.4 11
P6.5 12
P6.6 13
P6.7 14
IO
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The Port 6 pins also serve for alternate functions:
O
CS0
Chip Select 0 Output,
IO
CC0IO CAPCOM1: CC0 Capture Inp./Compare Output
O
CS1
Chip Select 1 Output,
IO
CC1IO CAPCOM1: CC1 Capture Inp./Compare Output
O
CS2
Chip Select 2 Output,
IO
CC2IO CAPCOM1: CC2 Capture Inp./Compare Output
O
CS3
Chip Select 3 Output,
IO
CC3IO CAPCOM1: CC3 Capture Inp./Compare Output
O
CS4
Chip Select 4 Output,
IO
CC4IO CAPCOM1: CC4 Capture Inp./Compare Output
I
HOLD
External Master Hold Request Input,
IO
CC5IO CAPCOM1: CC5 Capture Inp./Compare Output
I/O HLDA
Hold Acknowledge Output (master mode)
or Input (slave mode),
IO
CC6IO CAPCOM1: CC6 Capture Inp./Compare Output
O
BREQ Bus Request Output,
IO
CC7IO CAPCOM1: CC7 Capture Inp./Compare Output
Data Sheet
6
V1.0, 2002-03