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XC161CJ_02 Datasheet, PDF (62/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary
XC161
Derivatives
Preliminary
Electrical Parameters
Sample time and conversion time of the XC161’s A/D Converter are programmable. In
compatibility mode, the above timing can be calculated using Table 14.
The limit values for fBC must not be exceeded when selecting ADCTC.
Table 14 A/D Converter Computation Table1)
ADCON.15|14 A/D Converter
(ADCTC)
Basic Clock fBC
ADCON.13|12 Sample time
(ADSTC)
tS
00
fSYS / 4
00
tBC × 8
01
fSYS / 2
01
tBC × 16
10
fSYS / 16
10
tBC × 32
11
fSYS / 8
11
tBC × 64
1) These selections are available in compatibility mode. An improved mechanism to control the ADC input clock
can be selected.
Converter Timing Example:
Assumptions:
fSYS
Basic clock
fBC
Sample time
tS
Conversion 8-bit tC8
Conversion 10-bit tC10
= 40 MHz (i.e. tSYS = 25 ns), ADCTC = ‘01’, ADSTC = ‘00’.
= fSYS / 2 = 20 MHz, i.e. tBC = 50 ns.
= tBC × 8 = 400 ns.
= tS + 40 × tBC + 2 × tSYS = (400 + 2000 + 50) ns = 2.45 µs.
= tS + 48 × tBC + 2 × tSYS = (400 + 2400 + 50) ns = 2.85 µs.
Data Sheet
58
V1.0, 2002-03