XC161CJ_02 Datasheet, PDF (31/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
Functional Description
The XC161 also provides an excellent mechanism to identify and to process exceptions
or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware
traps cause immediate non-maskable system reaction which is similar to a standard
interrupt service (branching to a dedicated vector table location). The occurence of a
hardware trap is additionally signified by an individual bit in the trap flag register (TFR).
Except when another higher prioritized trap service is in progress, a hardware trap will
interrupt any actual program execution. In turn, hardware trap services can normally not
be interrupted by standard or PEC interrupts.
Table 5 shows all of the possible exceptions or error conditions that can arise during run-
time:
Table 5
Hardware Trap Summary
Exception Condition
Trap
Flag
Trap
Vector
Vector
Trap
Trap
Location¹⁾ Number Priority
Reset Functions:
–
– Hardware Reset
– Software Reset
– W-dog Timer Overflow
RESET
xx’0000_H 00_H
III
RESET
xx’0000_H 00_H
III
RESET
xx’0000_H 00_H
III
Class A Hardware Traps:
– Non-Maskable Interrupt NMI
NMITRAP xx’0008_H 02_H
II
– Stack Overflow
STKOF STOTRAP xx’0010_H 04_H
II
– Stack Underflow
STKUF STUTRAP xx’0018_H 06_H
II
– Software Break
SOFTBRK SBRKTRAP xx’0020_H 08_H
II
Class B Hardware Traps:
– Undefined Opcode
UNDOPC BTRAP
xx’0028_H 0A_H
I
– PMI Access Error
PACER BTRAP
xx’0028_H 0A_H
I
– Protected Instruction PRTFLT BTRAP
xx’0028_H 0A_H
I
Fault
– Illegal Word Operand ILLOPA BTRAP
xx’0028_H 0A_H
I
Access
Reserved
–
–
Software Traps
–
–
– TRAP Instruction
[2C_H –
3C_H]
Any
[xx’0000_H –
xx’01FC_H]
in steps
of 4_H
[0B_H –
0F_H]
Any
[00_H –
7F_H]
–
Current
CPU
Priority
1) _{Register VECSEG defines the segment where the vector table is located to.}
Data Sheet
27
V1.0, 2002-03