XC161CJ_02 Datasheet, PDF (63/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

Preliminary
5
Timing Parameters
XC161
Derivatives
Timing Parameters
5.1
Definition of Internal Timing
The internal operation of the XC161 is controlled by the internal master clock f_MC.
The master clock signal f_MC can be generated from the oscillator clock signal f_OSC via
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate f_MC.
This influence must be regarded when calculating the timings for the XC161.
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Figure 13 Generation Mechanisms for the Master Clock
Note: The example for PLL operation shown in Figure 13 refers to a PLL factor of 1:4,
the example for prescaler operation refers to a divider factor of 2:1.
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal f_CPU. The CPU clock can have the
same frequency as the master clock (f_CPU = f_MC) or can be the master clock divided by
two: f_CPU = f_MC / 2. This factor is selected by bit CPSYS in register SYSCON1.
The specification of the external timing (AC Characteristics) depends on the period of the
CPU clock, called “TCP”.
The other peripherals are supplied with the system clock signal f_SYS which has the same
frequency as the CPU clock signal f_CPU.
Data Sheet
59
V1.0, 2002-03