XC161CJ_02 Datasheet, PDF (69/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
Timing Parameters
Table 18 External Bus Cycle Timing (Operating Conditions apply)
Parameter
Symbol
Limits
Unit
min. max.
Output delay rising edge
Valid for: address, CS, BHE
tc₁₀ CC -1
6
ns
Output delay rising edge
Valid for: RD, WR, ALE
tc₁₁ CC -1
6
ns
Output delay rising edge
Valid for: write data
tc₁₂ CC -1
6
ns
Output delay falling edge
Valid for: address, CS, BHE
tc₁₃ CC -1
10
ns
Output delay falling edge
Valid for: RD, WR, ALE
tc₁₄ CC -1
10
ns
Output delay falling edge
Valid for: write data
tc₁₅ CC -1
10
ns
Output hold time
Valid for: address, CS, BHE
tc₁₆ CC –
2
ns
Output hold time
Valid for: RD, WR, ALE
tc₁₇ CC –
2
ns
Output hold time
Valid for: write data
tc₁₈ CC –
2
ns
Input setup time
Valid for: read data, READY
tc₁₉ SR 15
–
ns
Input hold time
Valid for: read data¹⁾, READY
tc₂₀ SR 5
–
ns
Turn off delay
tc₂₁ CC 0
5
ns
1) _{Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge}
of RD. Therefore address changes before the end of RD have no impact on (demultiplexed) read cycles. Read
data can be removed after the rising edge of RD.
Data Sheet
65
V1.0, 2002-03