XC161CJ_02 Datasheet, PDF (48/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
Functional Description
Table 7
Summary of the XC161’s Parallel Ports
Port
PORT0
PORT1
Control
Pad drivers
Pad drivers
Alternate Functions
Address/Data lines or data lines¹⁾
Address lines²⁾
Capture inputs or compare outputs,
Serial interface lines
Port 2
Pad drivers, Capture inputs or compare outputs,
Open drain,
Timer control signal,
Input threshold Fast external interrupt inputs
Port 3
Port 4
Pad drivers,
Open drain,
Input threshold
Pad drivers,
Open drain,
Input threshold
Timer control signals, serial interface lines,
Optional bus control signal BHE/WRH,
System clock output CLKOUT (or FOUT)
Segment address lines³⁾
CAN/SDLM interface lines⁴⁾
Port 5 ---
Analog input channels to the A/D converter,
Timer control signals
Port 6
Open drain,
Capture inputs or compare outputs,
Input threshold Bus arbitration signals BREQ, HLDA, HOLD,
Optional chip select signals
Port 7
Open drain,
Capture inputs or compare outputs,
Input threshold CAN/SDLM interface lines⁴⁾
Port 9
Pad drivers,
Open drain,
Input threshold
Capture inputs or compare outputs
CAN/SDLM interface lines⁴⁾,
IIC bus interface lines⁴⁾
Port 20 Pad drivers,
Open drain
Bus control signals RD, WR/WRL, READY, ALE,
External access enable pin EA,
Reset indication output RSTOUT
1) _{For multiplexed bus cycles.}
2) _{For demultiplexed bus cycles.}
3) _{For more than 64 Kbytes of external resources.}
4) _{Can be assigned by software.}
Data Sheet
44
V1.0, 2002-03