XC161CJ_02 Datasheet, PDF (25/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
Functional Description
The EBC also controls accesses to resources connected to the on-chip LXBus. The
LXBus is an internal representation of the external bus and allows accessing integrated
peripherals and modules in the same way as external components.
The TwinCAN module is connected and accessed via the LXBus.
3.3
Central Processing Unit (CPU)
The main core of the CPU consists of a 5-stage execution pipeline with a 2-stage
instruction-fetch pipeline, a 16-bit arithmetic and logic unit (ALU), a 32-bit/40-bit multiply
and accumulate unit (MAC), a register-file providing three register banks, and dedicated
SFRs. The ALU features a multiply and divide unit, a bit-mask generator, and a barrel
shifter.
Internal Program Memory ^PMU
System-Bus
CPU
Prefetch Unit
Branch Unit
CSP
IP
CPUCON1
CPUCON2
CPUID
VECSEG
TFR
FIFO
Return Stack
IFU
Injection/Exception
Handler
IDX0
IDX1
QX0
QX1
QR0
QR1
DPP0
DPP1
DPP2
DPP3
SPSEG
SP
STKOV
STKUN
+/-
Multiply Unit
+/-
MAH
MAC
+/-
MRW
MCW
MSW
MAL
ADU
Division Unit Bit-Mask-Gen.
Multiply Unit Barrel-Shifter
MDC
PSW
+/-
MDH
Zeros
MDL
Ones
ALU
2-Stage
Prefetch
Pipeline
5-Stage
Pipeline
IPIP
CP
R15
R1RR4 ^11R5415
GPRs ^R14
GPRs
GPRs
R1
R0RR01R1
R0
RF
Buffer
WB
DPRAM
address
R15
R14
GPRs
R1
R0
data in
data out
SRAM
DMU
Peripheral-Bus
System-Bus
Figure 4 CPU Block Diagram
Based on these hardware provisions, most of the XC161’s instructions can be executed
in just one machine cycle which requires 25 ns at 40 MHz CPU clock. For example, shift
and rotate instructions are always processed during one machine cycle independent of
Data Sheet
21
V1.0, 2002-03