XC161CJ_02 Datasheet, PDF (21/78 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary

XC161
Derivatives
Preliminary
Functional Description
3
Functional Description
The architecture of the XC161 combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resoures as well as external
resources (see Figure 3).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC161.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC161.
PSRAM
ProgMem
Flash
128 KBytes
OCDS
Debug Support
Osc / PLL RTC WDT
XTAL _{Clock Generation}
DPRAM
CPU
C166SV2-Core
DSRAM
EBC
XBUS Control
External Bus
Control
Interrupt & PEC
Interrupt Bus
Peripheral Data Bus
ADC
8/10-Bit
12/16
Channels
GPT
T2
T3
T4
ASC0 ASC1 SSC0 SSC1
(USART) (USART) (SPI) (SPI)
CC1
T0
T1
T5
T6 _{BRGen BRGen BRGen BRGen}
CC2
T7
T8
IIC SDLM
BRGen
Twin
CAN
AB
P 20 Port 9 P 7 Port 6
66 4
8
Port 5
16
Port 4
8
Port 3
15
Port 2
8
PORT1
16
PORT0
16
Figure 3 Block Diagram
MCB04323_x1.vsd
Data Sheet
17
V1.0, 2002-03