BTS54040-LBF_15 Datasheet, PDF (50/67 Pages) Infineon Technologies AG – SPI Power Controller

BTS54040-LBF
Serial Peripheral Interface (SPI)
CS “low” to “high” Transition
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in “low” state whenever chip select CS makes any transition, otherwise the
command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 9.5 for
further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CS pin
goes to “low” state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 9.5 for further information.
9.2
Daisy Chain Capability
The SPI of BTS54040-LBF provides daisy chain capability. In this configuration several devices are activated by
the same CS signal MCS. The SI line of one device is connected with the SO line of another device (see
Figure 27), in order to build a chain. The end of the chain is connected to the output and input of the master device,
MO and MI respectively. The master device provides the master clock MCLK which is connected to the SCLK line
of each device in the chain.
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCS
MCLK
SPI_DaisyChain.emf
Figure 27 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from SI line is shifted in each SCLK. The
bit shifted out occurs at the SO pin. After eight SCLK cycles, the data transfer for one device is finished. In single
chip configuration, the CS line must turn “high” to make the device acknowledge the transferred data. In daisy
chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using three devices in
daisy chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must turn “high”
(see Figure 28).
Data Sheet
50
Rev. 2.1, 2014-12-05