BTS54040-LBF_15 Datasheet, PDF (29/67 Pages) Infineon Technologies AG – SPI Power Controller

BTS54040-LBF
Power Stages
6.4
Power Stage Output
The power stages are built to be used in high side configuration (Figure 15).
The power DMOS switches with a dedicated slope, which is optimized in terms of electromagnetic emission
(EME). Defined slew rates allow lowest EME during PWM operation at low switching losses.
VS
V_DS
VS
GND
OUT
VOU T
PowerStage_Output.emf
Figure 15 Power Stage Output
6.4.1 Bulb and LED Mode
All four channels can be configured in bulb and LED mode via the SPI initialization registers LGCR when
SWCR.SWR = 0. The default state is LGCR.LEDn = 0. During LED mode the following parameters are changed for
an optimized functionality with LED loads: ON-state resistance R_DS(ON), switching timings (t_delay(ON), t_delay(OFF), t_ON,
t_OFF), slew rates dV/dt_ON and dV/dt_OFF, load current protections I_L(LIM) and current sense ratio k_ILIS.
6.4.2 Switching Resistive Loads
When switching resistive loads the following switching times and slew rates can be considered.
IN /
OUT.OUTn
V _{OU T}
90% of V_s
70% of V_s
t_ON
t _delay(ON)
30% of V_s
10% of V_s
dV /
d t_ON
Figure 16 Switching a Load (resistive)
t_OFF
t
t_{delay(OFF )}
dV /
d t_OFF
70% of V_s
30% of V_s
t
PowerStage_SwitchON.emf
Data Sheet
29
Rev. 2.1, 2014-12-05