BTS54040-LBF_15 Datasheet, PDF (15/67 Pages) Infineon Technologies AG – SPI Power Controller

BTS54040-LBF
Electrical Characteristics
Table 2 Absolute Maximum Ratings¹⁾ (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Number
ESD susceptibility HBM
V_ESD
-2
other pins vs. GND incl. OUT pins vs.
GND
2
kV
7)
HBM
P_4.1.49
ESD Resistivity to GND
V_ESD
-500
V
500
8)
CDM
P_4.1.51
ESD Resistivity Pin 1, 12, 13, 24
(corner pins) to GND
V_{ESD1, 12,}
13, 24
-750
1) Not subject to production test, specified by design.
V
750
8)
CDM
P_4.1.52
2) Device is mounted on an FR4 2s2p board according to Jedec JESD51-2,-5,-7 at natural convection; The product (chip and
package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 µm Cu, 2 * 35 µm Cu). Where
applicable, a thermal via array under the package contacted the first inner copper layer.
3) EOL tests according to AECQ100-012. Threshold limit for short circuit failures: 100 ppm. Please refer to the legal disclaimer
for short-circuit capability at the end of this document.
4) R_I is the internal resistance of the load dump pulse generator.
5) Current limitation is a protection feature. Protection features are not designed for continuous repetitive operation.
6) Pulse shape represents inductive switch OFF: I_D(t) = I_D(0) × (1 - t / t_pulse); 0 < t < t_pulse
7) ESD resistivity, HBM according to ANSI/ESDA/JEDEC JS-001-2010
8) ESD susceptibility, Charged Device Model “CDM” EIA/JESD22-C101 or ESDA STM5.3.1
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Data Sheet
15
Rev. 2.1, 2014-12-05