TLE9261-3QX Datasheet, PDF (43/186 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9261-3QX
• In case DLC is greater than 0, the data field of the received frame has at least one bit set in a bit position, where
also in the configured data mask in the corresponding bit position the bit is set.
• No error exists according to ISO 11898-1 excepting errors which are signalled in the ACK field and EOF field.
5.4.2.4 CAN Protocol Error Counter
The counter is incremented, when a bit stuffing, CRC or form error according to ISO11898-1 is detected. If a frame
has been received that is valid up to the end of the CRC field and the counter is not zero, the counter is
decremented.
If the counter has reached a value of 31, the following actions is performed on the next increment of this counter:
• The selective wake function is disabled,
• the CAN transceiver is woken,
• SYSERR is set and the error counter value = 32 can be read.
On each increment or decrement of the counter the decoder unit waits for at least 6 and most 10 recessive bits
before considering a dominant bit as new start of frame.
The error counter is enabled:
• whenever the CAN is in Normal Mode, Receive Only Mode or in WUF detection state.
The error counter is cleared under the following conditions:
• at the transition from WUF detection to WUP detection 1 (after t_SILENCE expiration, while SWK is correctly
enabled)
• When WUF detection state is entered (in this way the counter will start from 0 when SWK is enabled)
• At SBC or CAN rearming (when exiting the woken state)
• When the CAN Mode bits are selected ‘000’, ‘100’ (CAN OFF) or 0’01’ (Wake capable without SWK function
enabled)
• While CAN_FD_EN = ‘1’ and DIS_ERR_CNT = ‘1’
(the counter is cleared and stays cleared when these two bits are set in the SPI registers)
The Error Counter is frozen:
• after a wake-up being in woken state
The counter value can be read out of the bits ECNT.
Data Sheet
43
Rev. 1.1, 2014-09-26