TLE9261-3QX Datasheet, PDF (158/186 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9261-3QX
Serial Peripheral Interface
SWK_CDR_CTRL1
CDR Control 1 Register (Address 011 1100_B)
POR / Soft Reset Value: 0000 0100_B; Restart Value: 0000 xx0x_B
7
6
5
4
3
2
1
Reserved
r
Reserved
r
Reserved
r
Reserved SEL_FILT_1 SEL_FILT_0 Reserved
r
r
rw
rw
r
0
CDR_EN
rw
Field
Bits
Reserved 7:4
SEL_FILT 3:2
Reserved 1
CDR_EN 0
Type
r
rw
r
rw
Description
Reserved, always reads as 0
Select Time Constant of Filter
00_B , Time constant 8
01_B , Time constant 16 (default)
10_B , Time constant 32
11_B , adapt
distance between falling edges 2, 3 bit: Time constant 32
distance between f. edges 4, 5, 6, 7, 8 bit: Time constant 16
distance between falling edges 9, 10 bit: Time constant 8
Reserved, always reads as 0
Enable CDR
0_B , CDR disabled
1_B , CDR enabled
SWK_CDR_CTRL2
CDR Control 2Register (Address 011 1101_B)
POR / Soft Reset Value: 0000 0000_B; Restart Value: 0000 00xx_B
7
6
5
4
3
Reserved
r
Reserved
r
Reserved
r
Reserved
r
Reserved
r
2
1
0
Reserved
r
SEL_OSC_CL SEL_OSC_CL
K_1
K_0
r
rw
rw
Field
Bits
Reserved 7:2
SEL_OSC_C 1:0
LK
Type
r
rw
Description
Reserved, always reads as 0
Input Frequency for CDR module
See Table 34 and Table 35.
Table 34 Frequency Settings of Internal Clock for the CDR
SEL_OSC_CLK[1:0]
int. Clock for CDR
00
80 MHz
01
40 MHz
10
20 MHz
11
10 MHz
Data Sheet
158
Rev. 1.1, 2014-09-26