TLE9261-3QX Datasheet, PDF (123/186 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9261-3QX
Serial Peripheral Interface
15.3
SPI Programming
For the TLE9261-3QX, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read
Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual
configuration and status information, 8 data bits (BIT15...8) are used.
Writing, clearing and reading is done byte wise. The SPI status bits are not cleared automatically and must be
cleared by the microcontroller, e.g. if the TSD2 was set due to over temperature. The configuration bits will be
partially automatically cleared by the SBC - please refer to the individual registers description for detailed
information. During SBC Restart Mode the SPI communication is ignored by the SBC, i.e. it is not interpreted.
There are two types of SPI registers:
• Control registers: Those are the registers to configure the SBC, e.g. SBC mode, watchdog trigger, etc
• Status registers: Those are the registers where the status of the SBC is signalled, e.g. wake events, warnings,
failures, etc.
For the status registers, the requested information is given in the same SPI command in DO.
For the control registers, also the status of the respective byte is shown in the same SPI command. However, if
the setting is changed this is only shown with the next SPI command (it is only valid after CSN high) of the same
register.
The SBC status information from the SPI status registers, is transmitted in a compressed way with each SPI
response on SDO in the so called Status Information Field register (see also Figure 55). The purpose of this
register is to quickly signal the information to the microcontroller if there was a change in one of the SPI status
registers. In this way, the microcontroller does not need to read constantly all the SPI status registers but only
those registers, which were changed.
Each bit in the Status Information Field represents a SPI status register (see Table 33). As soon as one bit is set
in one of the status registers, then the respective bit in the Status Information Field register will be set. The register
WK_LVL_STAT is not included in the status Information field. This is listed in Table 33.
For Example if bit 0 in the Status Information Field is set to 1, one or more bits of the register 100 0001
(SUP_STAT_1) is set to 1. Then this register needs to be read in a second SPI command. The bit in the Status
Information Field will be set to 0 when all bits in the register 100 0001 are set back to 0.
Table 33 Status Information Field
Bit in Status
Information Field
Corresponding
Address Bit
0
100 0001
1
100 0010
2
100 0011
3
100 0100
4
100 0110
5
100 0000
6
101 0100
7
101 0101
Status Register Description
SUP_STAT_1: Supply Status -VSHS fail, VCCx fail, POR
THERM_STAT: Thermal Protection Status
DEV_STAT: Device Status - Mode before Wake, WD Fail,
SPI Fail, Failure
BUS_STAT: Bus Failure Status: CAN;
WK_STAT_1, WK_STAT_2: Wake Source Status;
Status bit is set as combinational OR of both registers
SUP_STAT_2: VCC1_WARN/OV, VCC3 Status
HS_OC_OT_STAT: High-Side Over Load Status
HS_OL_STAT: High-Side Open Load Status
Data Sheet
123
Rev. 1.1, 2014-09-26