TLE9261-3QX Datasheet, PDF (107/186 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9261-3QX
Supervision Functions
14.2
Watchdog Function
The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the
microcontroller stops serving the watchdog due to a lock up in the software.
Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN:
• Time-Out Watchdog (default value)
• Window Watchdog
The respective watchdog functions can be selected and programmed in SBC Normal Mode. The configuration
stays unchanged in SBC Stop Mode.
Please refer to Table 31 to match the SBC Modes with the respective watchdog modes.
Table 31 Watchdog Functionality by SBC Modes
SBC Mode
Watchdog Mode
Remarks
INIT Mode
Starts with Long Open Window Watchdog starts with Long Open Window after RO is
released
Normal Mode
WD Programmable
Window Watchdog, Time-Out watchdog or switched
OFF for SBC Stop Mode
Stop Mode
Watchdog is fixed or OFF
Sleep Mode
OFF
SBC will start with Long Open Window when entering
SBC Normal Mode.
Restart Mode
OFF
SBC will start with Long Open Window when entering
SBC Normal Mode.
The watchdog timing is programmed via SPI command. As soon as the watchdog is programmed, the timer starts
with the new setting and the watchdog must be served. The watchdog is triggered by sending a valid SPI-write
command to the watchdog configuration register. The trigger SPI command is executed when the Chip Select
input (CSN) becomes HIGH.
When coming from SBC Init, SBC Restart Mode or in certain cases from SBC Stop Mode, the watchdog timer is
always started with a long open window. The long open window (t_LW = 200ms) allows the microcontroller to run its
initialization sequences and then to trigger the watchdog via SPI.
The watchdog timer period can be selected via the watchdog timing bit field (WD_TIMER) and is in the range of
10 ms to 1000 ms. This setting is valid for both watchdog types.
The following watchdog timer periods are available:
• WD Setting 1: 10ms
• WD Setting 2: 20ms
• WD Setting 3: 50ms
• WD Setting 4: 100ms
• WD Setting 5: 200ms
• WD Setting 6: 500ms
• WD Setting 7: 1000ms
In case of a watchdog reset, SBC Restart or SBC Fail-Safe Mode is entered according to the configuration and
the SPI bits WD_FAIL are set. Once the RO goes HIGH again the watchdog immediately starts with a long open
window the SBC enters automatically SBC Normal Mode.
In SBC Software Development Mode the watchdog is OFF and therefore no reset and interrupt are generated due
to a watchdog failure.
Data Sheet
107
Rev. 1.1, 2014-09-26